Mitsubishi DS5000TK Betriebsanweisung Seite 128
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USER’S GUIDE
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128
EXPANDED DATA MEMORY READ Figure 15–5
PSEN
MACHINE CYCLE MACHINE CYCLE
ALE
PORT 0
PORT 2 PCH/P2 PCH/P2 DPH OR P2 OUT PCH/P2
PCL
OUT
DPL OR
RI, OUT
PCL
OUT
DATA
SAMPLED
DATA
SAMPLED
DATA
SAMPLED
RD
* PCL OUT if program memory also on Expanded Bus – float if not.
**PCH OUT if program memory also on Expanded Bus.
EXPANDED DATA MEMORY WRITE Figure 15–6
PSEN
MACHINE CYCLE MACHINE CYCLE
DATA
SAMPLED
DATA
SAMPLED
ALE
PORT 0
PORT2 PCH/P2 PCH/P2 DPH OR P2 OUT PCH/P2
PCL
OUT
PCL OUT
PC
OUT
DPL OR
RI, OUT
DATA OUT
(1)
(1)
(2) (2) (2)
WR
(1) PCL OUT if program memory also on Expanded Bus – float if not.
(2) PCH OUT if program memory also on Expanded Bus.
- TABLE OF CONTENTS 1
- SECTION 1: INTRODUCTION 2
- SOFTWARE SECURITY 2
- SEPARATE ADDRESS/DATA BUS 2
- LARGE NONVOLATILE MEMORY 3
- IN–SYSTEM LOADING 3
- HIGH RELIABILITY OPERATION 3
- PRODUCT DESCRIPTION 4
- 050396 4/173 5
- SECTION 2: SELECTION GUIDE 6
- 050396 6/173 7
- INTERNAL DATA BUS 8
- INTERNAL ADDRESS BUS 8
- 050396 8/173 9
- Watchdog Timer 10
- Resident Loader ROM 10
- Secure Microcontroller Memory 11
- Organization 11
- Internal Registers 11
- Programmer’s note 12
- Program and Data Memory 13
- 050396 13/173 14
- DS5000 Memory Map Control 16
- 050396 16/173 17
- 050396 17/173 18
- DS5001/DS5002 Memory Mapped 20
- Peripherals 20
- 050396 23/173 24
- 050396 25/173 26
- Special Function Registers 28
- PA3 PA2 PA1 PA0 RA32/8 ECE2 29
- POWER CONTROL REGISTER 31
- 050396 31/173 32
- TIMER CONTROL REGISTER 33
- TIMER MODE REGISTER 34
- SERIAL CONTROL REGISTER 35
- INTERRUPT ENABLE REGISTER 36
- INTERRUPT PRIORITY REGISTER 37
- DS5001 CRC REGISTER 38
- DS5001 MCON REGISTER 40
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- PROGRAM STATUS WORD REGISTER 42
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- INSTRUCTION SET 46
- Introduction 46
- Addressing Modes 46
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- Program Status Flags 48
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- DATA RETENTION 56
- BATTERY BACKED CIRCUITS 56
- BATTERY ATTACH PROCEDURE 57
- BATTERY LIFETIME 57
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- LITHIUM BATTERY USAGE 59
- FRESHNESS SEAL 59
- SECTION 7: POWER MANAGEMENT 60
- Idle Mode 60
- Stop Mode 61
- Voltage Monitoring Circuitry 62
- Power Fail Interrupt 63
- Total Power Failure 63
- Partial Power Failures 63
- SECTION 8: SOFTWARE CONTROL 65
- Timed Access 65
- TIMED ACCESS Figure 8–1 65
- 050396 65/173 66
- WATCHDOG TIMER Figure 8–2 68
- WATCHDOG TIMER CONTROL BITS 69
- CRC MEMORY VERIFICATION 69
- 050396 69/173 70
- CRC CODE EXAMPLE Figure 8–3 71
- SECTION 9: FIRMWARE SECURITY 72
- SECURITY OVERVIEW 72
- SECURITY LOCK 73
- RAM Memory 73
- Encrypted Memory 73
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- Encryption Algorithm 76
- Encryption Key 76
- Dummy Bus Access 77
- On–chip Vector RAM 78
- Self–Destruct Input 78
- Microprobe/Die Top Coating 78
- Random Number Generator 78
- Security Summary by Part 79
- 050396 79/173 80
- Change Code 81
- External Circuits 81
- Tamper Protection 81
- SECTION 10: RESET CONDITIONS 82
- Reset Sources 82
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- Power On Reset 84
- Power On Reset 85
- External Reset 85
- Watchdog Timer Reset 85
- Memory Map 86
- Interrupts 87
- Protection 88
- SECTION 11: INTERRUPTS 89
- INTERRUPT SOURCES 89
- External Interrupts 90
- Timer Interrupts 90
- Serial Port Interrupts 90
- Power–fail Warning Interrupt 90
- Simulated Interrupts 91
- INTERRUPT PRIORITIES 93
- INTERRUPT ACKNOWLEDGE 94
- 050396 94/173 95
- SECTION 12: PARALLEL I/O 96
- OVERVIEW 96
- PORT 1 FUNCTIONAL CIRCUITRY 97
- PORT 2 FUNCTIONAL CIRCUITRY 97
- PORT 3 FUNCTIONAL CIRCUITRY 98
- OUTPUT FUNCTIONS 98
- INPUT FUNCTION 99
- REPROGRAMMABLE PERIPHERAL 100
- CONTROLLER (RPC) 100
- RPC INTERRUPTS 101
- Bit Description: 102
- RPC PROTOCOL 103
- DMA OPERATION 103
- FUNCTIONAL DESCRIPTION 105
- Bit Description 105
- USER’S GUIDE 106
- 050396 105/173 106
- SECTION 14: SERIAL I/O 110
- FUNCTION DESCRIPTION 110
- SCON.2: RB8 112
- SCON.1: TI 112
- SCON.0: RI 112
- BAUD RATE GENERATION 112
- 050396 112/173 113
- 050396 113/173 114
- TRANSMIT TIMING: 115
- RECEIVE TIMING: 115
- ASYNCHRONOUS OPERATION 116
- Mode 2 and 3 117
- APPLICATION: SERIAL PORT 120
- INITIALIZATION 120
- SERIAL I/O OPERATING MODES 120
- 050396 120/173 121
- 050396 121/173 122
- 050396 122/173 123
- SECTION 15: CPU TIMING 124
- OSCILLATOR 124
- INSTRUCTION TIMING 125
- EXPANDED DATA MEMORY TIMING 129
- SECTION 16: PROGRAM LOADING 130
- INTRODUCTION 130
- INVOKING THE BOOTSTRAP LOADER 130
- DS5000 Series 131
- DS5001/DS5002 Series 131
- EXITING THE LOADER 131
- SERIAL PROGRAM LOAD MODE 133
- AUTO–BAUD RATE DETECTION 134
- COMMAND LINE INTERFACE 135
- COMMAND LINE SYNTAX 135
- COMMAND SUMMARIES 136
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- Xon/Xoff 138
- DS5002FP COMMANDS 138
- 050396 138/173 139
- INTEL HEX FILE FORMAT 140
- PARALLEL PROGRAM LOAD MODE 142
- PARALLEL PROGRAMMING CONCERNS 143
- RPC PROGRAM MODE OPERATION 143
- SECTION 17: REAL–TIME CLOCK 144
- DS1215 PHANTOM TIME CHIP 144
- 050396 144/173 145
- 050396 146/173 147
- REGISTERS 148
- SPECIAL BITS 148
- 050396 149/173 150
- MEMORY MAP 151
- TIME–OF–DAY ALARM 152
- 050396 152/173 153
- DS1283 RTC INTERRUPTS 154
- (DS1215 EXAMPLE) 155
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- 050396 156/173 157
- 050396 157/173 158
- (DS1283 EXAMPLE) 159
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- 050396 161/173 162
- 050396 162/173 163
- SECTION 18: TROUBLESHOOTING 164
- UNEXPLAINED DEVICE RESETS 164
- WRONG TIME 164
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- OGRAM BRANCHING 174
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